org 0x0

start:
    mov 0x20,#0
	mov 0x21,#0
	mov 0x22,#0
	
	setb 0x0 ;setb bit
	setb c
	mov 0x1,c
	
	mov 0x2,c
	clr c
	
	cpl c
	mov 0x3,c
	
	mov 0x4,c
	clr 0x4
	
	mov 0x5,c
	cpl 0x5
	
	setb 0x6
	clr  0x6
	mov c,0x6
	mov 0x7,c
	;logic anl
	setb 0x40
	setb c
	anl c,0x40
	mov 0x8, c
	
	anl c,/0x40
	mov 0x9,c
	;logic orl
	setb 0x40
	setb c
	orl  c,0x40
	mov 0x10,c
	
	orl c,/0x40
	mov 0x11,c
	;jc/jnc
	setb c
	jnc next0
	jc next0
	sjmp $
next0:
	clr c
	jc next1
	jnc next1
	sjmp $
next1:
	;jb/jnb
	setb 0x40
	jnb 0x40,next2
	jb 0x40,next2
	sjmp $
next2:
	clr c
	jb 0x40,next3
	jnb 0x40,next3
	sjmp $
next3:
	;jbc
	clr 0x40
	setb 0x41
	jbc 0x40,next4
	jbc 0x41,next5
	sjmp $
next4:
	sjmp $
next5:
	mov 0x12,c
	sjmp $
;for test
REG_SP     EQU 0x1000
REG_A      EQU 0x1001
REG_B      EQU 0x1002
REG_PSW    EQU 0x1003
REG_PC     EQU 0x1004
REG_DPTR   EQU 0x1005
CYCLE      EQU 0x1006
REG_R0     EQU 0x2000
REG_R1     EQU 0x2001
REG_R2     EQU 0x2002
REG_R3     EQU 0x2003
REG_R4     EQU 0x2004
REG_R5     EQU 0x2005
REG_R6     EQU 0x2006
REG_R7     EQU 0x2007
REG_END    EQU 0x2FFF
	org 0x600
	dw 0x20,0x0f
	dw 0x21,0x01
	dw 0x22,0x03
	dw REG_SP,    0x7
	dw REG_A,     0x0
	dw REG_B,     0x0
	dw REG_PC,    0x6b
	dw REG_DPTR,  0x0
	dw CYCLE,     75
	dw REG_R0,    0x0
	dw REG_R1,    0x0
	dw REG_R2,    0x0
	dw REG_R3,    0x0
	dw REG_R4,    0x0
	dw REG_R5,    0x0
	dw REG_R6,    0x0
	dw REG_R7,    0x0
	dw REG_END
end
	